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Standard EEPROM ICs
SLx 24C01/02/P 1/2 Kbit (128/256 x 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection ModeTM
Data Sheet 1998-07-27
SLx 24C01/02/P Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 5 15 4, 5 5 11, 12 21 19 25 25 25
I2C Bus
Current Version: 1998-07-27 06.97 Subjects (major changes since last revision)
3 5 15 4, 5 - 11, 12 21 24 25 25 25
Text was changed to "Typical programming time 5 ms for up to 8 bytes". WP = VCC protects the upper half entire memory. Figure 11: second command byte is a CSR and not CSW. CS0, CS1 and CS2 were replaced by n.c. The paragraph "Chip Select (CS0, CS1, CS2)" was removed completely. The erase/write cycle is finished latest after 10 8 ms. The write or erase cycle is finished latest after 10 4 ms. "Capacitive load ..." were added. Some timings were changed. The line "erase/write cycle" was removed. Chapter 8.4 "Erase and Write Characteristics" has been added.
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. Edition 1998-07-27 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1/2 Kbit (128/256 x 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection ModeTM
SLx 24C01/02/P
Features * Data EEPROM internally organized as 128/256 bytes and 16/32 pages x 8 bytes * Page protection mode, flexible page-by-page hardware write protection - Additional protection EEPROM of 16/32 bits, 1 bit per data page P-DIP-8-4 - Protection setting for each data page by writing its protection bit - Protection management without switching WP pin * Low power CMOS * VCC = 2.7 to 5.5 V operation * Two wire serial interface bus, I2C-Bus compatible * Filtered inputs for noise suppression with Schmitt trigger P-DSO-8-3 * Clock frequency up to 400 kHz * High programming flexibility - Internal programming voltage - Self timed programming cycle including erase - Byte-write and page-write programming, between 1 and 8 bytes - Typical programming time 5 ms for up to 8 bytes * High reliability - Endurance 106 cycles1) - Data retention 40 years1) - ESD protection 4000 V on all pins * 8 pin DIP/DSO packages * Available for extended temperature ranges - Industrial: - 40 C to + 85 C - Automotive: - 40 C to + 125 C
1)
Values are temperature dependent, for further information please refer to your Siemens Sales office.
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Ordering Information Type SLA 24C01-D/P SLA 24C01-S/P SLA 24C01-D-3/P SLA 24C01-S-3/P SLE 24C01-D/P SLE 24C01-S/P SLA 24C02-D/P SLA 24C02-S/P SLA 24C02-D-3/P SLA 24C02-S-3/P SLE 24C02-D/P SLE 24C02-S/P Ordering Code Package Q67100-H3547 Q67100-H3495 Q67100-H3546 Q67100-H3494 Q67100-H3545 Q67100-H3493 Q67100-H3542 Q67100-H3537 Q67100-H3541 Q67100-H3536 Q67100-H3540 Q67100-H3535 P-DIP-8-4 P-DIP-8-4 P-DIP-8-4 P-DIP-8-4 P-DIP-8-4 P-DIP-8-4 Temperature Voltage
- 40 C ... + 85 C 4.5 V...5.5 V - 40 C ... + 85 C 2.7 V...5.5 V - 40C ... + 125 C 4.5 V...5.5 V - 40 C ... + 85 C 4.5 V...5.5 V - 40 C ... + 85 C 2.7 V...5.5 V - 40C ... + 125 C 4.5 V...5.5 V
P-DSO-8-3 - 40 C ... + 85 C 4.5 V...5.5 V P-DSO-8-3 - 40 C ... + 85 C 2.7 V...5.5 V P-DSO-8-3 - 40C ... + 125 C 4.5 V...5.5 V P-DSO-8-3 - 40 C ... + 85 C 4.5 V...5.5 V P-DSO-8-3 - 40 C ... + 85 C 2.7 V...5.5 V P-DSO-8-3 - 40C ... + 125 C 4.5 V...5.5 V
Other types are available on request - Temperature range (- 55 C ... + 150 C) - Package (die, wafer delivery) 1 Pin Configuration P-DIP-8-4
N.C. N.C. N.C. 1 2 3 4 8 7 6 5
IEP02515
P-DSO-8-3
V CC
WP SCL SDA
N.C. N.C. N.C. VSS 1 2 3 4 8 7 6 5
IEP02514
VCC WP SCL SDA
VSS
Figure 1 Pin Configuration (top view)
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Pin Definitions and Functions Table 1 Pin No. 1, 2, 3 4 5 6 7 8 Pin Description Serial Clock (SCL) The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge. Serial Data (SDA) SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to VCC. Write Protection (WP) WP switched to VSS allows normal read/write operations. WP switched to VCC protects the entire EEPROM against changes (hardware write protection). Additionally write protection is managed by a protection bit associated to each page. (refer to chapter 7 Page Protection ModeTM) Symbol N.C. Function Not connected Ground Serial bidirectional data bus Serial clock input Write protection input Supply voltage
VSS
SDA SCL WP
VCC
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2
Description
The SLx 24C01/02/P device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 128/256 x 8 bit. The data memory is divided into 16/ 32 pages. The 8 bytes of a page can be programmed simultaneously. Each page may be protected individually against changes by its associated protection bit. The device conforms to the specification of the 2-wire serial I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents. The device operates at 5.0 V 10% with a maximum clock frequency of 400 kHz and at 2.7 ... 4.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V type (VCC = 4.5 ... 5.5 V) with two temperature ranges for industrial and automotive applications and as 3 V type (VCC = 2.7 ... 5.5 V) for industrial applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.
V SS V CC
WP
Chip Address Control Logic Start/ Stop Logic SCL SDA Serial Control Logic
Programming Control H.V. Pump
Address Logic
X DEC
EEPROM
Page Prot. Bit EEPROM
Page Logic Y DEC
Dout/ACK
IEB02531
Figure 2 Block Diagram
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3
I2C-Bus Characteristics
The SLx 24C01/02/P devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave.
V CC
Slave 1 SCL Master SDA
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
V CC
IES02183
Figure 3 Bus Configuration Master Slave Device that initiates the transfer of data and provides the clock for both transmit and receive operations. Device addressed by the master, capable of receiving and transmitting data.
Transmitter The device with the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a low level wins. Receiver The device with the SDA as input is defined as the receiver.
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The conventions for the serial clock line and the bidirectional data line are shown in figure 4.
SCL
1
2
8
9
1
9
SDA START Condition Data allowed to Change
ACK Acknowledge
ACK STOP Condition
IED02128
Figure 4 I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Validation and Transfer of Acknowledge ACK Standby Mode in which the bus is not busy (no serial transmission, no programming): both clock (SCL) and data line (SDA) are in high state. The device enters the standby mode after a STOP condition or after a programming cycle. High to low transition of SDA when SCL is high, preceding all commands. Low to high transition of SDA when SCL is high, terminating all communications. A STOP condition initiates an EEPROM programming cycle. A STOP condition after reading a data byte from the EEPROM initiates the Standby mode. A successful reception of eight data bits is indicated by the receiver by pulling down the SDA line during the following clock cycle of SCL (ACK). The transmitter on the other hand has to release the SDA line after the transmission of eight data bits. The EEPROM as the receiving device responds with an acknowledge, when addressed. The master, on the other side, acknowledges each data byte transmitted by the EEPROM and can at any time end a read operation by releasing the SDA line (no ACK) followed by a STOP condition. Data must change only during low SCL state, data remains valid on the SDA bus during high SCL state. Nine clock pulses are required to transfer one data byte, the most significant bit (MSB) is transmitted first.
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START Condition STOP Condition
Acknowledge
Data Transfer
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4
Device Addressing and EEPROM Addressing
After a START condition, the master always transmits a Command Byte CSW or CSR. After the acknowledge of the EEPROM a Control Byte follows, its content and the transmitter depend on the previous Command Byte. The description of the Command and Control Bytes is shown in table 2. Command Byte Selects operation: the least significant bit b0 is low for a write operation (Chip Select Write Command Byte CSW) or set high for a read operation (Chip Select Read Command Byte CSR). In both Command Bytes, the bit positions b3 to b1 are left undefined. Following CSW (b0 = 0): contains the seven or eight lower bits of the EEPROM address (EEA) bit A6 or A7 to A0, or an additional command byte for the handling of the protection bit. Following CSR (b0 = 1): contains the data read out, transmitted by the EEPROM. The EEPROM data are read as long as the master pulls down SDA after each byte in order to acknowledge the transfer. The read operation is stopped by the master by releasing SDA (no acknowledge is applied) followed by a STOP condition. Table 2 Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM Definition b7 CSW CSR EEA 1 1 b6 b5 0 0 1 1 b4 b3 b2 b1 b0 0 0 x x x x x x 0 1 Chip Select for Write Chip Select for Read Function
Control Byte
A7 A6 A5 A4 A3 A2 A1 A0 EEPROM address
The device has an internal address counter which points to the current EEPROM address. The address counter is incremented - after a data byte to be written has been acknowledged, during entry of further data byte - during a byte read, thus the address counter points to the following address after reading a data byte.
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The timing conventions for read and write operations are described in figures 5 and 6.
Command Byte (CSW) SCL
1 2 3 4 5 6 7 8 9 10
Data Transfer to EEPROM
11 12 13 14 15 16 17 18
SDA
1
0
1
0
X
X
X
0
A7
A6
A5
A4
A3
A2
A1 A0 ACK
START from Master
Acknowledge from EEPROM
Acknowledge from EEPROM
IED02255
Figure 5 Timing of the Command Byte CSW
Command Byte (CSR) SCL
1 2 3 4 5 6 7 8 9
Data Transfer from EEPROM
10 11 12 13 14 15 16 17 18
SDA
1
0
1
0
X
X
X
1
ACK
ACK
START from Master
Acknowledge from EEPROM
Acknowledge from Master
IED02185
Figure 6 Timing of the Command Byte CSR
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5
Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW. Depending on the state of the Write Protection pin WP and of the Protection Bits (refer to chapter 7 Page Protection ModeTM) either one byte (Byte Write) or up to 8 bytes (Page Write) are modified in one programming procedure. 5.1 Byte Write After a START condition the master transmits the Chip Select Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following byte with the EEPROM address (A0 to A6 or A7) is loaded into the address counter of the EEPROM and acknowledged by the EEPROM. Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer. Then the master applies a STOP condition which starts the internal programming procedure. The data bytes are written in the memory location addressed in the EEA byte (A0 to A6 or A7). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to "1". With the next internal step, the addressed byte is written according to the contents of the buffer.
S T A Command Byte EEPROM Address R CSW EEA T S 0 A C K A C K A C K
IED02129
Address Setting
Transmission of Data Programming Cycle
Bus Activity Master SDA Line Bus Activity EEPROM
Data Byte
S T O P P
Figure 7 Byte Write Sequence The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 Acknowledge Polling).
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5.2
Page Write The page write procedure is the same as the byte write procedure up to the first data byte. In a page write instruction however, entry of the EEPROM address byte EEA is followed by a sequence of one to maximum eight data bytes with the new data to be programmed. These bytes are transferred to the internal page buffer of the EEPROM. The first entered data byte will be stored according to the EEPROM address n given by EEA (A0 to A6 or A7). The internal address counter is incremented automatically after the entered data byte has been acknowledged. The next data byte is then stored at the next higher EEPROM address. EEPROM addresses within the same page have common page address bits A2 through A6 or A7. Only the respective three least significant address bits A0 through A2 are incremented, as all data bytes to be programmed simultaneously have to be within the same page. The master stops data entry by applying a STOP condition, which also starts the internally timed erase/write cycle. In the first step, all selected bytes are erased to "1". With the next internal step, the addressed bytes are written according to the contents of the page buffer.
Address Setting
Transmission of Data
Programming Cycle
Those bytes of the page that have not been addressed are not included in the programming.
S T A Command Byte EEPROM Address R CSW EEA n T S 0 A C K A C K A C K A C K A C K
IED02280
Bus Activity Master SDA Line Bus Activity EEPROM
Data Byte n
Data Byte n+1
Data Byte n+7
S T O P P
Figure 8 Page Write Sequence The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 Acknowledge Polling).
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5.3
Acknowledge Polling
During the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter. To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. If the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue.
Internal Programming Procedure
Send Start
Send CS-Byte
Acknowledge from EEPROM received? Yes Next Operation
No
IED02131
Figure 9 Flow Chart "Acknowledge Polling"
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STOP from Master initiates erase/write cycle START from Master CSR SDA P S 1 S CSR 1 S S CSR 1 P
Acknowledge of EEPROM indicates complete erase/ write cycle STOP from Master initiates erase/write cycle START from Master CSW SDA P S 0 S e.g. STOP condition CSW 0 S S CSW 0 P
Acknowledge of EEPROM indicates complete erase/ write cycle
IED02166
Figure 10 Principle of Acknowledge Polling
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6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR. 6.1 Random Read
Random read operations allow the master to access any memory location. Address Setting The master generates a START condition followed by the command byte CSW. The receipt of the CSW-byte is acknowledged by the EEPROM with a low on the SDA line. Now the master transmits the EEPROM address (EEA) to the EEPROM and the internal address counter is loaded with the desired address. After the acknowledge for the EEPROM address is received, the master generates a START condition, which terminates the initiated write operation. Then the master transmits the command byte CSR for read, which is acknowledged by the EEPROM. During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter. During the following clock cycle the masters releases the bus and then transmits the STOP condition.
Transmission of CSR
Transmission of EEPROM Data STOP Condition from Master
Bus Activity Master SDA Line Bus Activity EEPROM
S T A Command Byte EEPROM Address R EEA n CSW T S 0 A C K A C K
S T A Command Byte R CSR T S 1 A C K Data Byte
S T O P P
IED02133
Figure 11 Random Read
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6.2
Current Address Read
The EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an interrupt).
Transmission of CSR
For a current address read the master generates a START condition, which is followed by the command byte CSR (chip select read). The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line. During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter. During the following clock cycle the masters releases the bus and then transmits the STOP condition.
Transmission of EEPROM Data STOP Condition from Master
Bus Activity Master SDA Line Bus Activity EEPROM
S T A Command Byte R CSR T S 1 A C K Data Byte
S T O P P
IED02132
Figure 12 Current Address Read
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6.3
Sequential Read
A sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The internal address counter is incremented by one during each data byte transmission. A sequential read allows the entire memory to be read during one read operation. In the SLx 24C02/P, after the highest addressable memory location is reached, the internal address pointer "rolls over" to the address 0 and the sequential read continues. In the SLx 24C01/P, there is no "roll over". The transmission is terminated by the master by releasing the SDA line (no acknowledge) and generating a STOP condition (see figure 13).
Bus Activity Master SDA Line Bus Activity EEPROM
S T A Command Byte R CSW T S 1 A C K Data Byte n
A C K
A C K
S T O P P
Data Byte n+1
Data Byte n+x
IED02134
Figure 13 Sequential Read
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7
Page Protection ModeTM
Each page (8 bytes) in the Data Memory can be protected against unintended data changes by an associated protection bit. The protection bit memory consists of an additional EEPROM of 16/32 bits (figure 14). Data in the Data Memory can be modified only if the assigned protection bit is erased (logical state "1"). After writing the data bytes to a page, the protection is achieved by writing the associated protection bit (logical state "0"). Further changes in the data in a protected page is possible only after erasing the protection bit.
Data Memory Area
Protection Bit Memory Area
Page 0 Page 1 Page 2 Page 3 . . . Page n 0 1 2 3 4 5 6 7 Byte
0 1 2 3 . . . n Bit
IED02141
Figure 14 Data Page and Assigned Protection Memory A special procedure to write or erase a protection bit guarantees proper activation or deactivation respectively of page protection. For protection bit write or erase, all 8 data bytes of the respective page have to be entered for a second time. The data then are compared internally with the data to be protected, and in case of identity the protection bit is written or erased respectively.
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7.1
Protection Bit Handling
The bits of the protection memory can be addressed directly for reading or programming. A protection bit address corresponds to the lowest address within the respective page (A3 to A6 or A7, A0 to A2 = zero). The status of each protection bit is sensed internally. A written state ("0") prevents programming in the associated page. If an already protected memory page is accidentally addressed for programming, the programming procedure is suppressed. The conventional I2C-Bus protocol allows data bytes to be read and programmed only. Therefore an independent instruction sequence for addressing and manipulation of protection bits is implemented. For protection bit instructions, the command byte CSW with its preceding START condition followed by the associated control byte has to be entered twice (figures 15 through 17). The first command byte CSW is followed by the control byte EEA with the bit/page address A0 through A2 always at zero. The second CSW is required for entering a control byte CTx for protection bit manipulation. The three control bytes for read, write or erase of a protection bit are listed below (table 3): Table 3 Control Byte for Protection Bit Manipulation Address Name CTR CTW CTE Definition b7 x x x b6 x x x b5 x x x b4 x x x b3 x x x b2 x x x b1 0 0 1 b0 0 1 1 Protection bit read Protection bit write Protection bit erase Function
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7.2
Protection Bit Write and Erase
For writing or erasing a protection bit, the data of the respective page have to be known by the master. The data of the page are not affected by the write or erase procedure of the protection bit. The I2C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for protection bit erase.
Bus Activity Master SDA Line Bus Activity EEPROM
S T Command A Byte R CSW T S
0
EEPROM Address EEA n
0000
S T Command A Byte R CSW T S A C K
0
Control Byte CTW
01
Data Byte n
Data ... Data Byte n+1 Byte n+7
S T O P P
A C K
A C K
A C K
A C K
A C K
A C K
IED02142
Figure 15 Sequence for Protection Bit Write
Bus Activity Master SDA Line Bus Activity EEPROM
S T Command A Byte R CSW T S
0
EEPROM Address EEA n
0000
S T Command A Byte R CSW T S A C K
0
Control Byte CTE
11
Data Byte n
Data ... Data Byte n+1 Byte n+7
S T O P P
A C K
A C K
A C K
A C K
A C K
A C K
IED02143
Figure 16 Sequence for Protection Bit Erase The first command byte CSW followed by the control byte EEA addresses the page to be protected. The second command byte CSW (identical content of first CSW) is followed by the control byte CTW = 01H for protection bit write or CTE = 03H for protection bit erase. Depending on CTx, the addressed protection bit will be either written or erased.
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The control byte CTx is followed by 8 parameter bytes identical to the 8 data bytes of the page to be protected or unprotected. The data of the first entered byte must be identical to the data byte stored at the lowest address of the current page. The other 7 bytes have to be identical to the bytes stored in ascending address order within the same page. A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to low (acknowledge ACK). After verification of the last byte, the bit programming procedure is initiated by the STOP condition. Programming is started only if all 128 bits of a page have been verified successfully. If bit programming has taken place, the address counter points to the uppermost address of the respective page. The write or erase cycle is finished latest after 4 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the write or erase cycle (refer to chapter 5.3 Acknowledge Polling).
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7.3
Protection Bit Read
The byte sequence for random bit read is shown in figure 17.
Bus Activity Master SDA Line Bus Activity EEPROM
S T Command A Byte R CSW T S
0
EEPROM Address EEA n
0000
S T Command A Byte R CSW T S A C K
0
Control Byte CTR
00 b
A C K
b
A C K
b
S T O P P ... A C K
IED02139
A C K
A C K
A Data C Byte n K
Data Byte n+1
b = Protection Bit
Figure 17 Byte Sequence for Protection Bit Read The first command byte CSW followed by the control byte EEA addresses the protection bit to be read. The second command byte CSW is followed by the control byte 00H for protection bit read. The first bit (MSB) of the transferred byte is the protection bit of the addressed page. The other 7 bits are not valid. The page protection status is indicated as following Protection Bit = 1: A normal write operation changes the data in the associated page Protection Bit = 0: The data in the associated page are protected against changes. If the master acknowledges a byte with a low state of the SDA line, the protection bit of the next page can be read as the first bit of the following byte. If the master releases the SDA line, a STOP condition has to complete the read procedure. Any number of bytes with a page protection status at the first bit position can be requested by the master. If the bit of the uppermost page has been addressed, the counter has its overflow to the lowest address according to the first page.
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8
Electrical Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. 8.1 Absolute Maximum Ratings
Stresses above those listed here may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Operating temperature Storage temperature Supply voltage All inputs and outputs with respect to ground ESD protection (human body model) 8.2 DC Characteristics Symbol min. Supply voltage Limit Values typ. max. 5.5 5.5 1 3 50 0.1 0.1 - 0.3 10 10 V V mA A A A 5 V type 3 V type 4.5 2.7 Units Test Condition range 1 (industrial) range 2 (automotive) Limit Values - 40 to + 85 - 40 to + 125 - 65 to + 150 - 0.3 to + 7.0 - 0.3 to VCC + 0.5 4000 Units C C C V V V
Parameter
VCC VCC ICC ISB ILI ILO VIL
Supply current1) (write) Standby current2) Input leakage current Output leakage current Input low voltage
VCC = 5 V; fc = 100 kHz
Inputs at VCC or VSS
VIN = VCC or VSS VOUT = VCC or VSS
0.3 x VCC V
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8.2
DC Characteristics (cont'd) Symbol min. Limit Values typ. max. 0.7 x VCC Units Test Condition
Parameter Input high voltage Output low voltage Input/output capacitance (SDA) Input capacitance (other pins)
VIH VOL CI/O
VCC + 0.5 V
0.4 83) V pF
IOL = 3 mA; VCC = 5 V IOL = 2.1 mA; VCC = 3 V VIN = 0 V; VCC = 5 V
CIN
63)
pF
VIN = 0 V; VCC = 5 V
Capacitive load Cb for each bus line
1) 2) 3)
400
pF
The values for ICC are maximum peak values Valid over the whole temperature range This parameter is characterized only
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8.3
AC Characteristics Symbol Limit Values Limit Values Units
Parameter
VCC = 2.7-5.5 V
min. max. 100 4.7 4.0 1000 300 4.7 4.0 200 0 0.1 100 4.0 4.7 50 100 4.5
VCC = 4.5-5.5 V
min. 1.2 0.6
1) 1)
max. 400 kHz s s 300 300 ns ns s s ns s 0.9 s ns s s 100 ns
fSCL tlow Clock pulse width low thigh Clock pulse width high tR SDA and SCL rise time tF SDA and SCL fall time tSU.STA Start set-up time tHD.STA Start hold time tSU.DAT Data in set-up time tHD.DAT Data in hold time tAA SCL low to SDA data out valid tDH Data out hold time tSU.STO Stop set-up time Time the bus must be free before tBUF
SCL clock frequency a new transmission can start SDA and SCL spike suppression tl time at constant inputs
1)
0.6 0.6 100 0 0.1 50 0.6 1.2 50
The minimum rise and fall times can be calculated as follows: 20 + (0.1/pF) x Cb [ns] Example: Cb = 100 pF tR = 20 + 0.1 x 100 [ns] = 30 ns
8.4
Erase and Write Characteristics Symbol Limit Values VCC = 2.7-5.5 V typ. max. 8 4 4 5 2.5 2.5 Limit Values Units VCC = 4.5-5.5 V typ. 5 2.5 2.5 max. 8 4 4 ms ms ms
Parameter
Erase + write cycle (per page) Erase page protection bit Write page protection bit
tWR
Semiconductor Group
25
1998-07-27
SLx 24C01/02/P
tR tF t LOW t HIGH
SCL
t SU.STA t HD.STA
t SU.DAT t HD.DAT t SU.STO t BUF
SDA In Start Condition
t AA
t DH
Stop Condition
SDA Out
IED02127
Figure 18 Bus Timing Data
Semiconductor Group
26
1998-07-27
SLx 24C01/02/P
9
Package Outlines P-DIP-8-4 (Plastic Dual In-line Package)
P-DSO-8-3 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 27
Dimensions in mm 1998-07-27
GPS09032
GPD05583

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